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| L99PD08 SPI control diagnosis interface device for VIPowerTM M0-5 and M0-5E high side drivers Features I I I I I I I I I I I I I 8 channel VIPower driver and diagnostics device Supports analog and digital VIPower status readback 8 independent PWM channels Selectable PWM base clock (2 external, one internal) Programmable PWM turn on phase shift Programmable diagnostic thresholds (analog VIPower) Programmable over temperature latch off for enhanced HSD short circuit reliability Limp home safety mode ST-SPI interface protocol for data communication External enable pin for low power mode Detailed and filtered diagnostic for each channel Direct multiplexed VIPower status / current sense feedback Supply voltage 3.3 or 5.0 V (two pins) LQFP32 Description The device has integrated several functions which save job load of the microcontroller and save necessary connections to the microcontroller. It's possible to connect analog and digital high side drivers (HSD) to the device and control them via SPI interface. A synchronous detailed diagnostics feature is integrated. The device has 8 outputs to the HSD with the possibility to be driven either by steady state ON/OFF mode or by PWM. Two clock inputs used as base frequency to generate the PWM signal internally are provided. The outputs are fully independent and can also be driven with phase shift to improve characteristics of power net during the inrush phase. The device has 8 current sense (CS)/status (ST) pins connected to the HSD to run diagnostics. The index of ST/CS pin corresponds to the input connected to the same HSD channel (ST0/CS0 with OUT0, ST1/CS1 with OUT1 ...). Applications I Exterior and interior automotive light system Table 1. Summary device Order codes Package Tube LQFP32 L99PD08 Tape and reel L99PD08TR April 2010 Doc ID 15872 Rev 3 1/41 www.st.com 1 Contents L99PD08 Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 2.5 2.6 2.7 ST-SPI: SCK, SDI, SDO, CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CLK_IN0, CLK_IN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LHOMEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output 0 to 7 (OUT0 ... OUT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status/current sense inputs (ST0/CS0 ... ST7/CS7) . . . . . . . . . . . . . . . . . 9 Multiplexed status/current sense output (MUX_ST/CS) . . . . . . . . . . . . . . . 9 VDDIO, VCORE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7.1 2.7.2 5.0 volt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 volt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 2.9 2.10 2.11 GND (2 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Faultn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 4 Device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 4.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 6.2 SPI timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.1 6.2.2 6.2.3 6.2.4 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial data output (SDO) Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/41 Doc ID 15872 Rev 3 L99PD08 6.3.1 6.3.2 6.3.3 6.3.4 Contents General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4 SPI - control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 7.2 7.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LQFP32 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Doc ID 15872 Rev 3 3/41 List of tables L99PD08 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Summary device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output switches/fault pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current sense/status inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MUX_ST/CS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current MUX_ST/CS ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current sense diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LHOMEN and SYNC pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CSN timeout/CLK_INx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Global status byte: description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ROM memory map (access with OC0 and OC1 set to `1') . . . . . . . . . . . . . . . . . . . . . . . . . 29 Control register, hex00 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ON_OFF register, hex01 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DEV_TYPE register, hex02 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PWM_EN register, hex03 (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CLK_SEL register, hex04 (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ASDT register, hex05 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DET_DIAG register, hex06 (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 BLK_TIME1 register, hex07 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 BLK_TIME2 register, hex08 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TD_SENSE register, hex09 (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CFR register, hex0A (RW-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 OLOVL_TH_1 register, hex0B (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 OLOVL_TH_2 register, hex0C (RW-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DUTY_CH 0 - DUTY_CH 7 Registers, hex10 - hex17 (RW-Type) . . . . . . . . . . . . . . . . . . 34 PHASE_CH 0 - PHASE_CH7 Registers, hex18 - hex1F (RW-Type) . . . . . . . . . . . . . . . . 34 CHANNEL_FB Registers, hex2E (R-Type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AUX_STATUS Registers, hex2F (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OT_FAULT Registers, hex30 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OL_FAULT Registers, hex31 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STK_FAULT Registers, hex32 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 OVL_FAULT Registers, hex33 (RC-Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4/41 Doc ID 15872 Rev 3 L99PD08 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Application example block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinning of device in LQFP-32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Example for SYNC pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CS pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ST pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MUX_ST/CS ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SDO status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LQFP32 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LQFP32 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 LQFP32 tray shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Doc ID 15872 Rev 3 5/41 Block diagram L99PD08 1 Figure 1. Vbat Block diagram Application example block diagram LHOMEN 10k Vreg 5V VDDIO VDD diagnostics 3 4k7 4k7 Vbat_SWITCH 10k 4k7 4k7 VCORE3 Vreg 3.3V CHANNEL0 ST0/CS0 OUT0 100 IN1 IN2 CS1 CS2 OUT1 OUT2 VIP MUX_ST/CS 1k 2k7 ST1/CS1 OUT1 100 ....... VDD 10k 1k 1k 1k VNxxxAx ..... .... Microcontroller 10k 1k 1k FAULT CLK_IN0 CLK_IN1 EN SYNC 10k CONTROL LOGIC Vbat_SWITCH 4k7 4k7 ST6/CS6 OUT6 VDD 4k7 IN1 IN2 VDD 4k7 4k7 OUT1 OUT2 1k 1k 1k 1k CSN SCK SDI SDO SPI CHANNEL7 ST7/CS7 OUT7 4k7 ST1 ST2 VIP VNxxx GND 6/41 Doc ID 15872 Rev 3 L99PD08 Pin definitions and functions 2 Pin definitions and functions Table 2. Pin 1 2 3, 13 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin definition and function Symbol CLK_IN0 CLK_IN1 GND VDDIO FAULTN SYNC MUX_ST/CS VCORE3 SCK SDI SDO CSN EN N.C. LHOMEN ST7/CS7 OUT7 ST6/CS6 OUT6 ST5/CS5 OUT5 ST4/CS4 OUT4 ST3/CS3 OUT3 ST2/CS2 OUT2 ST1/CS1 OUT1 ST0/CS0 OUT0 PWM clock input 0 PWM clock input 1 Common ground I/O and 3.3 V voltage regulator supply (3.3 V or 5 V) Failure on HSD or communication error Output of OUT0-OUT7 signals, selected by control register Output from ST/CS multiplexer Core supply voltage (3.3 V only) ST-SPI - serial clock input ST-SPI - serial data input ST-SPI - serial data output ST-SPI - chip select input Enable pin Not connected Active mode pull-up supply - limp home Input from HSD status / current sense pin Output to High side driver - channel 7 Input from HSD status / current Sense pin Output to high side driver - channel 6 Input from HSD status / current sense pin Output to high side driver - channel 5 Input from HSD status / current sense pin Output to high side driver - channel 4 Input from HSD status / current sense pin Output to high side driver - channel 3 Input from HSD status / current sense pin Output to high side driver - channel 2 Input from HSD status / current sense pin Output to high side driver - channel 1 Input from HSD status / current sense pin Output to high side driver - channel 0 Function Doc ID 15872 Rev 3 7/41 Pin definitions and functions Figure 2. Pinning of device in LQFP-32 package L99PD08 ST0/CS0 ST1/CS1 ST2/CS2 27 32 31 30 29 28 26 CLK_IN0 CLK_IN1 GND VDDIO FAULTN SYNC MUX_ST/CS VCORE3 1 2 3 4 5 6 7 8 25 ST3/CS3 OUT0 OUT1 OUT2 OUT3 L99PD08 LQFP32 PreDiag Device 24 23 22 21 20 19 18 17 OUT4 ST4/CS4 OUT5 ST5/CS5 OUT6 ST6/CS6 OUT7 ST7/CS7 10 11 12 13 14 EN 15 N.C. 2.1 ST-SPI: SCK, SDI, SDO, CSN A 16-bit SPI interface is used to control the device. The communication interface is activated by pulling CSN to low. The SDI is captured with the positive edge of SCK and the data is shifted out at SDO at the negative edge of SCK. A CSN timeout is implemented. 2.2 CLK_IN0, CLK_IN1 These pins are used to run the two internal PWM base frequency counters to generate the output PWM. Each channel can be programmed as steady state ON/OFF output or a PWM output through the PWM_EN (Addr: hex03) SPI register. During PWM mode, the PWM signal can be generated either from CLK_IN0 or CLK_IN1 as base counter, selected through the SPI register CLK_SEL (Addr: hex04). Phase shift and duty cycle are set through the dedicated registers DUTY_CHx (Addr: hex10 - hex17) and PHASE_CHx (Addr: hex18 - hex1F). 8/41 Doc ID 15872 Rev 3 LHOMEN 16 9 GND SDO SCK CSN SDI L99PD08 Pin definitions and functions The output PWM period is a factor of 256 of the frequency applied on CLK_INx signal. If the external clock signal is not available or is below fPWM(min) , the device will fallback to an internal PWM frequency generator fPWM of approximately 122Hz periode. 2.3 LHOMEN This pin allows connecting the output pull-down resistor for LIMP HOME mode. This pin is pulled to VDDIO in normal mode and is pulled low in case of failure (RESET and FAIL SAVE mode). If power supply VDDIO is not connected, LHOMEN becomes weak low (LIMP HOME mode). 2.4 Output 0 to 7 (OUT0 ... OUT7) True open drain outputs are used to drive the High Side Driver inputs. These lines must have a pull-up resistor connected either to a separate supply or LHOMEN signal if LIMP HOME is supported. These outputs are high impedance during RESET, Fail Safe modes and during SW Reset. 2.5 Status/current sense inputs (ST0/CS0 ... ST7/CS7) Those inputs are used to take the status or current sense information from DIGITAL or ANALOG HSD and provide information to the internal diagnosis. Every output has to correspond to the same HSD channel like the ST/CS input (OUT0 with ST0/CS0, OUT1 with ST1/CS1, ...). Status of digital channels have to have an external pull-up resistor (4.7 kOhm) and a series protection resistor of 4.7 kOhm to STx/CSx, current sense signals of analog channels have to be connected to STx/CSx pins through a 100 Ohm reverse battery protection resistor. The HSD type which is connected to the device (digital or analog) must be selected through the register DEV_TYPE (Addr: hex02). 2.6 Multiplexed status/current sense output (MUX_ST/CS) The MUX_ST/CS Pin reflects the status or current sense information corresponding to the channel selected in the control register bits MUX_EN, MUX_A, B, C (Addr: hex00; Bit 7-4). This pin delivers up to 3 mA at 2.7 V. It is recommended to use a 1.6k to 2.7kOhm external resistor to ground for the maximum dynamic range. The best choice for the external resistor depends on the Rdson class of the analog current sense HSD and of the loads. If the multiplexer is disabled the MUX_ST/CS pin is in tristate condition. 2.7 VDDIO, VCORE3 The digital voltage supply of the device is internally limited to 3.3 V. In order to support also the 5 V supply voltages a linear internal voltage regulator can be used. Doc ID 15872 Rev 3 9/41 Pin definitions and functions L99PD08 2.7.1 5.0 volt operation The voltage regulator input is available at the terminal VDDIO, the output is available at VCORE3. In the 5V operation mode it is recommended to attach a decoupling capacitor on VCORE3 to stabilize the regulator. Due to the limited current capability of this regulator no external loads should be attached on VCORE3. 2.7.2 3.3 volt operation In applications with 3.3 V supply only, both, VDDIO and VCORE3 have to be attached (shorted) to the local supply. If the internal supply (VCORE3) is below the threshold of the internal power-and-reset circuit, the device is in standby mode. The device is in low power consumption and no SPI communications are possible. 2.8 GND (2 pins) These two pins are the GND voltage supply of the device and have to be connected externally. 2.9 Faultn This active low pin indicates any internal error reported by the device. This can be a High Side Driver failure or a communication error. In fault condition this open drain output is set to low, while during reset it is left open. This pin has to be connected to a pull up resistor. 2.10 SYNC The SYNC pin reflects the OUTx corresponding to the channel selected in the control register bits MUX_EN, MUX_A, B, C (Addr: hex00; Bit 7-4). If the multiplexer is disabled the SYNC pin is actively pulled low. Figure 3. Example for SYNC pin functionality OUT0 OUT1 SYNC Channel 0 selected Channel 1 selected 10/41 Doc ID 15872 Rev 3 L99PD08 Pin definitions and functions 2.11 EN With this pin pulled high, the device leaves low power mode. An internal pull down resistor guarantees the OFF condition when not connected. Doc ID 15872 Rev 3 11/41 Device mode L99PD08 3 Table 3. Mode Device mode Device modes Source Actions All registers are cleared All registers are cleared All registers are cleared Active Active CS-timer SPI state Outputs state High-Z fail safe High-Z fail safe High-Z fail safe ChipResetLHOMEN bit 1 1 0 LOW(1) 1 0 VDDIO LOW(1) LOW(1) Power down Standby Low VCORE3 EN = `0' CSNTO(2) / LHOMEN bit =`0' SW reset Not active Not active No comm. No comm. Fail save Normal LHOMEN-bit = `1' Active Active Normal 1. Max. sink current can only be guaranteed for VCORE3 VCORE3min. Therefore an external pull down is recommended. 2. ChipSelectNot-TimeOut Note: To leave FAIL SAVE the LHOMEN-bit in ControlRegister (Addr.: hex00, Bit 0) has to be set to `1'. FAIL SAVE is reentered by either ChipSelectNot-TimeOut (CSNTO) or SW-Reset (in both cases LHOME-bit is automatically reset) or setting this bit to `0' via SPI access. To stay in normal mode a rising edge has to be generated at CSN within every timeframe programmed in the control register (Addr.: hex00, Bit 3,2). Else a CSNTO is detected and FAIL SAVE entered. When SDI is stuck to GND the device enters automatically FAIL SAVE. When SDI is stuck to logical high level then the device receives a SW-Reset and enters FAIL SAVE. A read of ROM address Addr.: hex3F is detected as stuck to logical high level. In FAIL SAVE the SYNC pin is logical high. 12/41 Doc ID 15872 Rev 3 L99PD08 Figure 4. Device state diagram Device mode POWER DOWN STANDBY = '1' EN EN '0' =' = 0' EN FAIL SAVE LHOMEN-bit = '1' NORMAL LHOMEN-bit = '0' CSN-TimOut SW-Reset Doc ID 15872 Rev 3 13/41 Absolute maximum ratings L99PD08 4 Table 4. Symbol VCORE3 VDDIO Absolute maximum ratings Absolute maximum ratings Parameter Stabilized supply voltage Stabilized supply voltage Value -0.3 to 3.6 -0.3 to 5.5 -0.3 to VDDIO + 0.3 Unit V V EN, SCK, DI, CSN, CLK_INx Digital input / output voltage / DO, SYNC, LHOMEN OUT 1-8, FAULTN MUX ST/CS ST/CS 1-8 ST/CS 1-8 Output current (open drain) Output current Input current Input Voltage V 10 1 10 -14 to 6.5 mA mA mA V Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit. 4.1 ESD protection Table 5. ESD protection Parameter All pins Value 2 Unit kV Note: HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A HBM with all unzapped pins grounded 4.2 Operating junction temperature Table 6. Symbol Tj Rthmax Operating junction temperature Parameter operating junction temperature Value -40 to 150 90 Unit C K/W 14/41 Doc ID 15872 Rev 3 L99PD08 Electrical characteristics 5 Electrical characteristics VDDIO = 3.15 V to 5.25 V, VCORE3 = 3.15 V to 3.4 V, Tj = -40 to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 7. Symbol Supply Parameter Operating supply voltage range 5V Operating supply voltage range 3.3V Regulated output voltage range Iout = 2 mA, VDDIO=5.0 V VDDIO DC supply current VDDIO = 5.0 V, EN=5.0 V, All IOs open/floating VDDIO = 5.0 V = CSN, EN = 0 (standby mode), All IOs open/floating VDDIO = 3.3 V = CSN, EN = 0 (standby mode), all IOs open/floating Test condition Min. 4.75 3.15 3.15 Typ. 5.0 3.3 3.3 1 Max. 5.25 3.35 3.35 5 Unit V V V mA VDDIO VCORE3 ICORE VDDIO quiescent supply current 0 1 A VDDIO quiescent supply current 0 6 A Table 8. Symbol VPOR OFF VPOR ON VPOR hyst Undervoltage detection Parameter Power-on reset threshold Power-on reset threshold Power-on reset hysteresis Test condition VCORE3 increasing VCORE3 decreasing VPOR OFF - VPOR ON 2.3 0.3 Min. Typ. Max. 3.0 Unit V V V Table 9. Symbol VEN VCLAMPP VCLAMPN EN pin Parameter High voltage Positive clamping voltage Negative clamping voltage Test condition EN = VCORE3 rising/falling Min. 1.0 7 -20 Typ. Max. 2.0 10 -16 Unit V V V Doc ID 15872 Rev 3 15/41 Electrical characteristics Table 10. Symbol VOUTsat Ileak VIL(1) VIH(1) VCLAMPP VCLAMPN L99PD08 Output switches/fault pin Parameter Output saturation voltage Output leakage current Input low voltage Input high voltage Positive clamping voltage Negative clamping voltage Test condition IOUT1-8 = 1 mA OUTx off, VOUT = 5.0 V VCORE3 = 3.3 V, increasing VCORE3 = 3.3 V, decreasing 1.2 7 -20 10 -16 Min. Typ. 0.1 50 Max. 0.3 70 2.0 Unit V A V V V V 1. Output switches read back only Table 11. Symbol VSAT IINHST IINLST VCLAMPP VCLAMPN tTD_SENSE low tTD_SENSE high tCS_OFF tCS_filter tON-state tON-OFF_trans ttrans_valid tOFF-state tST_filter Current sense/status inputs Parameter Input saturation voltage ST input current threshold to detect high level ST input current threshold to detect low level Positive clamping voltage Negative clamping voltage Filter time for TD_SENSE = `0' blanking (tCS_filter included) Filter time for TD_SENSE = `1' blanking (tCS_filter included) CS filter OFF time CS diagnosis filter time ST diagnosis ON-State blanking time ST diagnosis ON-OFF transition blanking time ST diagnosis transition valid time ST diagnosis OFF-State blanking time ST diagnosis filter time Blanking time for inrush current CHx1,0 = [0,1], 15ms Test condition IIN = 6 mA IIN = 50 A Increasing Decreasing Min. 2.4 0.8 80 50 8 -20 300 600 1.0 54 200 20 20 1.0 54 15 70 200 Typ. 3.0 1.0 110 85 Max. 3.5 1.4 140 110 11 -16 600 1000 1.55 111 350 33 190 1.55 111 21 100 280 Unit V V A A V V s s ms s s s s ms s ms ms ms tblank Blanking time for inrush current CHx1,0 = [1,0], 70ms Blanking time for inrush current CHx1,0 = [1,1], 200ms 16/41 Doc ID 15872 Rev 3 L99PD08 Figure 5. CS pin timing Electrical characteristics CS-pin filter and blank timings : BLK_TIME (CHx-1;CHx-0) = 00" Addr hex07,hex08 t CS_filter t TD_SENSE t CS_OFF t CS_filter Diagnosis in on-state blanked Diagnosis in on-state enabled Short to battery blanked Short to battery enabled Figure 6. ST pin timing ST-pin filter and blank timings : BLK_TIME (CHx-1;CHx-0) = 00" Addr hex07,hex08 tST_filter tON-state tON-OFF_trans t trans_valid t OFF-state Diagnosis in on-state blanked Diagnosis in on-state enabled OL/OT discrimination Diagnosis blanked Short to battery blanked tST_filter Short to battery enabled Table 12. Symbol VOUT1mA VOUT3mA VOUT5mA VOUT1mA MUX_ST/CS output Parameter Current mode output saturation voltage Current mode output saturation voltage Current mode output saturation voltage Voltage mode output saturation voltage Test condition IOUT = 1 mA, VCORE3 = 3.3 V IOUT = 3 mA, VCORE3 = 3.3 V IOUT = 5 mA, VCORE3 = 3.3 V IOUT = 1 mA, VCORE3 = 3.3 V Min. 3.0 2.7 2.6 3.1 Typ. Max. Unit V V V V Doc ID 15872 Rev 3 17/41 Electrical characteristics Table 13. Symbol L99PD08 Current MUX_ST/CS ratio Parameter current MUX_ST/CS ratio @ ICS = 2.04 mA current MUX_ST/CS ratio @ ICS = 70% * 2.04 mA current MUX_ST/CS ratio @ ICS = 35% * 2.04 mA current MUX_ST/CS ratio @ ICS = 5% * 2.04 mA current MUX_ST/CS ratio @ ICS = 3.4 mA current MUX_ST/CS ratio @ ICS = 70% * 3.4 mA current MUX_ST/CS ratio @ ICS = 35% * 3.4 mA current MUX_ST/CS ratio @ ICS = 5% * 3.4 mA current MUX_ST/CS ratio @ ICS = 5.1 mA current MUX_ST/CS ratio @ ICS = 70% * 5.1 mA current MUX_ST/CS ratio @ ICS = 35% * 5.1 mA current MUX_ST/CS ratio @ ICS = 5% * 5.1 mA current MUX_ST/CS ratio @ ICS = 10.2 mA current MUX_ST/CS ratio @ ICS = 70% * 10.2 mA current MUX_ST/CS ratio @ ICS = 35% * 10.2 mA current MUX_ST/CS ratio @ ICS = 5% * 10.2 mA Test condition Min. 0.790 0.780 CFL = 0, OLOVL[1,0] = 0,0 0.760 0.700 0.470 0.470 CFL = 0, OLOVL[1,0] = 0,1 0.470 0.450 0.310 0.310 CFL = 0, OLOVL[1,0] = 1,0 0.300 0.300 0.150 0.150 CFL = 0, OLOVL[1,0] = 1,1 0.150 0.150 0.167 0.167 0.180 0.180 0.333 0.333 0.167 0.167 0.360 0.370 0.180 0.180 0.500 0.500 0.333 0.333 0.530 0.550 0.350 0.350 0.833 0.833 0.500 0.500 0.930 0.980 0.520 0.520 Typ. 0.833 0.833 Max. 0.910 0.910 Unit - k0_00 k0_01 k0_10 k0_11 18/41 Doc ID 15872 Rev 3 L99PD08 Table 13. Symbol Electrical characteristics Current MUX_ST/CS ratio (continued) Parameter current MUX_ST/CS ratio @ ICS = 204 A current MUX_ST/CS ratio @ ICS = 70% * 204 A Test condition Min. 8.20 8.15 CFL = 1, OLOVL[1,0] = 0,0 8.10 7.60 7.30 4.70 4.70 CFL = 1, OLOVL[1,0] = 0,1 4.70 4.45 4.20 3.10 3.10 CFL = 1, OLOVL[1,0] = 1,0 3.10 3.10 2.80 Typ. 8.33 8.33 8.33 8.33 8.33 5.00 5.00 5.00 5.00 5.00 3.33 3.33 3.33 3.33 3.33 Max. 8.90 8.90 8.90 8.90 8.90 5.30 5.35 5.35 5.45 5.45 3.50 3.50 3.50 3.50 3.70 Unit - k1_00 current MUX_ST/CS ratio @ ICS = 35% * 204 A current MUX_ST/CS ratio @ ICS = 5% * 204 A current MUX_ST/CS ratio @ ICS = 5 A current MUX_ST/CS ratio @ ICS = 340 A current MUX_ST/CS ratio @ ICS = 70% * 340 A k1_01 current MUX_ST/CS ratio @ ICS = 35% * 340 A current MUX_ST/CS ratio @ ICS = 5% * 340 A current MUX_ST/CS ratio @ ICS = 5 A current MUX_ST/CS ratio @ ICS = 510 A current MUX_ST/CS ratio @ ICS = 70% * 510 A k1_10 current MUX_ST/CS ratio @ ICS = 35% * 510 A current MUX_ST/CS ratio @ ICS = 5% * 510 A current MUX_ST/CS ratio @ ICS = 5 A Doc ID 15872 Rev 3 19/41 Electrical characteristics Table 13. Symbol L99PD08 Current MUX_ST/CS ratio (continued) Parameter current MUX_ST/CS ratio @ ICS = 1.02 mA current MUX_ST/CS ratio @ ICS = 70% * 1.02 mA Test condition Min. 1.50 1.50 CFL = 1, OLOVL[1,0] = 1,1 1.50 1.50 1.25 Typ. 1.67 1.67 1.67 1.67 1.67 Max. 1.80 1.80 1.80 1.80 1.90 Unit - k1_11 current MUX_ST/CS ratio @ ICS = 35% * 1.02 mA current MUX_ST/CS ratio @ ICS = 5% * 1.02 mA current MUX_ST/CS ratio @ ICS = 5 A Figure 7. MUX_ST/CS ratio Current MUX_ST/CS Ratio: Kx_xx Kx_xx max Kx_xx typ Kx_xx min ICS 5% ICS =5A ICS_ref 35% ICS_ref 70% I CS_ref 20/41 Doc ID 15872 Rev 3 L99PD08 Table 14. Symbol Electrical characteristics Current sense diagnostic thresholds Parameter Test condition CFL = 1, OLOVL[1,0] = 0,0 Open-load detection current threshold (1:1) CFL = 1, OLOVL[1,0] = 0,1 CFL = 1, OLOVL[1,0] = 1,0 CFL = 1, OLOVL[1,0] = 1,1 CFL = 0, OLOVL[1,0] = 0,0 Open-load detection current threshold (1:10) CFL = 0, OLOVL[1,0] = 0,1 CFL = 0, OLOVL[1,0] = 1,0 CFL = 0, OLOVL[1,0] = 1,1 CFL = 1, OLOVL[1,0] = 0,0 Overload detection current threshold (1:1) CFL = 1, OLOVL[1,0] = 0,1 CFL = 1, OLOVL[1,0] = 1,0 CFL = 1, OLOVL[1,0] = 1,1 CFL = 0, OLOVL[1,0] = 0,0 Overload detection current threshold (1:10) CFL = 0, OLOVL[1,0] = 0,1 CFL = 0, OLOVL[1,0] = 1,0 CFL = 0, OLOVL[1,0] = 1,1 Min. 3.5 3.5 6 31 35 35 60 310 90 190 300 490 0.9 1.9 3.0 4.9 4.9 Typ. 5 5 10 40 50 50 100 400 120 240 360 600 1.2 2.4 3.6 6.0 6.0 Max. 6.5 6.5 13 47 65 65 130 470 150 290 420 720 1.5 2.9 4.2 7.2 7.2 mA mA A A A Unit IOPLD IOVLD IOVTEMP Over temperature Table 15. Symbol VOL VOH VCLAMPP VCLAMPN LHOMEN and SYNC pin Parameter Output low voltage Output high voltage Positive clamping voltage Negative clamping voltage Test condition Iout = 5 mA Iout = 5 mA VDDIO - 1.0 7 -20 Min. Typ. 10 -16 Max. 0.4 Unit V V V V An external pull down of 10 kOhm is recommended to guarantee sufficient low level in case of VDDIO is not connected. Doc ID 15872 Rev 3 21/41 SPI L99PD08 6 SPI VDDIO = 3.15 V to 5.25 V, VCORE3 = 3.15 V to 3.4 V, Tj = -40 to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin Table 16. Symbol DC characteristics Parameter Test condition SDI, SCK, CSN, CLK_INx Min Typ Max Unit VIL VIH RCSN in RSCK in RSDI in Input low voltage Input high voltage CSN pull up resistor SCK pull down resistor SDI pull down resistor VDDIO = 3.3 V, increasing VDDIO = 3.3 V, decreasing 1.2 110 50 50 50 7 -20 SDO 150 100 100 100 2.0 V V 210 150 150 150 10 -16 k k k k V V RCLK_INx CLK_INx pull down resistor VCLAMPP Positive clamping voltage VCLAMPN Negative clamping voltage VOL VOH Output low voltage Output high voltage Iout = 5 mA Iout = 5 mA VDDIO 0.4 - 1.0 7 -20 10 -16 V V V V VCLAMPP Positive clamping voltage VCLAMPN Negative clamping voltage Table 17. Symbol fSCK tCSNQV tCSNQT tSCKQV tSCSN tSSDI tHSCK tLSCK Dynamic characteristics Parameter Serial clock frequency CSN falling until SDO valid CSN rising until SDO tristate SCK rising until SDO valid CSN setup time before SCK rising SDI setup time before SCK rising Minimum SCK high time Minimum SCK low time Cout = 50 pF Cout = 50 pF Cout = 50 pF 125 20 100 100 Test condition Min Typ 1 Max 4 50 150 100 Unit MHz ns ns ns ns ns ns ns 22/41 Doc ID 15872 Rev 3 L99PD08 Table 17. Symbol tHCSN tSSCK SPI Dynamic characteristics (continued) Parameter Minimum CSN high time SCK setup time before NCS rising Test condition Min 5 50 Typ Max Unit s ns 6.1 Figure 8. SPI timing parameter definition SPI timing diagram tHCSN CSN tCSNQV SDO t SCSN SCK tSSDI SDI tHSCK Data in tLSCK Data in Data out tSCKQV Data out tSSCK tCSNQT Table 18. Symbol CSN timeout/CLK_INx timings Parameter CSN timeout 50ms Test condition Min 50 100 200 400 4.8 5.2 5.0 7.0 Typ Max 72 145 285 570 6.2 9.2 102.4 Unit ms ms ms ms kHz kHz kHz tCSN_TIMEOUT CSN timeout 100ms CSN timeout 200ms CSN timeout 400ms fFAIL fOK_ fCLK_INx CLK_INx fail detected CLK_INx ok detected CLK_INx frequency range 6.2 Functional description of the SPI This device uses a 16 bit SPI slave protocol structured according to the ST SPI Standard to communicate with a microcontroller. Doc ID 15872 Rev 3 23/41 SPI Figure 9. SPI frame structure Write Operation CSN L99PD08 SDI MSB Command Byte (8 bit) Data (8 bit) LSB MSB LSB SDO Global Status Byte (8 bit) Data (previous content of register ) MSB LSB Read Operation CSN SDI MSB Command Byte (8 bit) All 0 (8 bit) LSB MSB LSB SDO Global Status Byte (8 bit) Data (8 bit) MSB LSB 6.2.1 Serial clock (SCK) This input signal provides the timing of the serial interface. Data present at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK). Data on Serial Data Out (SDO) is shifted out at the falling edge of Serial Clock (SCK). The writing to the selected data input register is only enabled if exactly one frame length is transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored and a SPI frame error is signaled in the Global Status register. This safety function is implemented to avoid an unwanted activation of output stages by a wrong communication frame. Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. 24/41 Doc ID 15872 Rev 3 L99PD08 SPI 6.2.2 Serial data input (SDI) This input is used to transfer data serially into the device. It receives the data to be written. Values are latched on the rising edge of Serial Clock (SCK). 6.2.3 Serial data output (SDO) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). SDO also reflects the status of the 6.2.4 Chip select not (CSN) When this input signal is High, the communication interface of the device is deselected and Serial Data Output (SDO) is high impedance. Driving this input Low enables the communication. The communication must start and stop on a Low level of Serial Clock (SCK). A CSN timeout is implemented. 6.3 6.3.1 SPI communication flow General description The proposed SPI communication is based on a standard SPI interface structure using CSN (Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock) signal lines. Each communication frame consists of an instruction byte which is followed by 1 data byte. The data returned on DO within the same frame always starts with the 6.3.2 Command byte Each communication frame starts with a command byte. It consists of an operating code which specifies the type of operation ( Command byte MSB Op code OC1 OC0 A5 A4 A3 Address A2 A1 A0 LSB Note: OCx: Operating Code Ax: Address Doc ID 15872 Rev 3 25/41 SPI L99PD08 6.3.3 Operating code definition Table 20. OC1 0 0 1 1 Operating code definition OC0 0 1 0 1 Description The 6.3.4 Table 21. Bit Global status byte Global status byte 7 Global error flag 6 Communication error 5 No (chip reset or communication error) 4 Over temp/ over load 3 2 Openload 1 0 Name n/a STK_ON Fail save Table 22. Global status byte: description Polarity Active high Comment Logical OR combination of all failures in the Name Global error flag Communication error Active high Set if the number of clock cycles during CSN low does not match with the specified frame width. SDI stuck at '0' will force the LHOME-bit to be cleared and is not signaled as a communication error. SDI stuck at '1' will lead to a software reset and is therefore not signaled as a communication error. FAIL SAVE is entered in both cases. 26/41 Doc ID 15872 Rev 3 L99PD08 Table 22. Global status byte: description (continued) Polarity Comment SPI Name No (chip reset or communication error) Active low Activated by all internal reset events which change the device state or configuration registers (e.g. software reset, VCORE3 undervoltage, etc.). This bit is initially '0' and will be set to '1' by a valid SPI communication to any register. Set when over temp and/or over load failure is detected by the diagnosis function Not implemented Set when open-load failure is detected by the diagnosis function Set when SHORT TO BATTERY is detected by the diagnosis function (OFF state diagnosis) Indicates if the device is in FAIL SAVE (defined state) Over temp/ over load n/a Open-load Active high 0 Active high STK_ON Active high Fail save Active high Figure 10. SDO status CSN high to low and SCK stays low: status information of data bit 0 (fault condition) is transfered to SDO CSN time SCK time SDI time SDI: data is not accepted SDO GEF time SDO: status information of data bit 0 (Global Error Flag) will stay as long CSN is low Note: In case of a status change during an SPI transmission this status will not be read and therefore not cleared in case of a clear command. Due to the internal mechanism of loading the status data into the shift register a possible inconsistency between the GlobalErrorRegister and the read StatusRegister can occur. In this case, the data in the Status Register is always the more actual data. Doc ID 15872 Rev 3 27/41 SPI L99PD08 6.4 Table 23. Address hex00 hex01 hex02 hex03 hex04 hex05 hex06 hex07 hex08 hex09 hex0A hex0B hex0C hex10 hex11 hex12 hex13 hex14 hex15 hex16 hex17 hex18 hex19 hex1A hex1B hex1C hex1D hex1E hex1F hex2E hex2F hex30 hex31 SPI - control and status register RAM memory map Name CTRL ON_OFF DEV_TYPE PWM_EN CLK_SEL ASDT DET_DIAG_N BLK_TIME1 BLK_TIME2 TD_SENSE CFR OLOVL_TH1 OLOVL_TH2 DUTY_CH 0 DUTY_CH 1 DUTY_CH 2 DUTY_CH 3 DUTY_CH 4 DUTY_CH 5 DUTY_CH 6 DUTY_CH 7 PHASE_CH 0 PHASE_CH 1 PHASE_CH 2 PHASE_CH 3 PHASE_CH 4 PHASE_CH 5 PHASE_CH 6 PHASE_CH 7 CHANNEL_FB AUX_STATUS OT_FAULT OL_FAULT Access Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Read/clear Read/clear Read/clear Control register Switch On or OFF the output Device type register (write protected if channel ON) PWM mode enable register Clock input signal selection register Automatic shutdown register Detailed diagnosis disable Blank time 1 (write protected if channel ON) Blank time 2 (write protected if channel ON) Td_SENSE (write protected if channel ON) Current feedback ratio register Open-load/Over load 1 threshold settings Open-load/Over load 2 threshold settings PWM duty cycle selection - channel O0 PWM duty cycle selection - channel O1 PWM duty cycle selection - channel O2 PWM duty cycle selection - channel O3 PWM duty cycle selection - channel O4 PWM duty cycle selection - channel O5 PWM duty cycle selection - channel O6 PWM duty cycle selection - channel O7 Phase shift setting register - channel O0 Phase shift setting register - channel O1 Phase shift setting register - channel O2 Phase shift setting register - channel O3 Phase shift setting register - channel O4 Phase shift setting register - channel O5 Phase shift setting register - channel O6 Phase shift setting register - channel O7 Read back of OUTx state Auxiliary warning flag registers Overtemperature failure register Open-load in ON state failure register Content 28/41 Doc ID 15872 Rev 3 L99PD08 Table 23. Address hex32 hex33 SPI RAM memory map (continued) Name STK_FAULT OVL_FAULT Access Read/clear Read/clear Content STK ON/OLOFF failure register Overload failure register Table 24. Address 0x00 0x01 0x02 0x03 0x3E ROM memory map (access with OC0 and OC1 set to `1') Name ID header Version ProducCode1 ProducCode2 SPI frame ID Access Read only Read only Read only Read only Read only Content hex43 (device class ASSP, 2 additional information bytes) hex00 (engineering samples) (ST-SPI) hex25 (ST-SPI) hex50 (ST-SPI) hex01 SPI-Frame-ID register (ST-SPI) Table 25. Bit 7 MUX_EN Control register, hex00 (RW-Type) Bit 6 MUX_C Bit 5 MUX_B Bit 4 MUX_A Bit 3 CS_MON1 Bit 2 CS_MON0 Bit 1 Bit 0 LHOMEN MUX_EN 0 the multiplexer MUX ST/CS pin is inactive (tristate) 1 the multiplexer MUX ST/CS pin is active (default) MUX_A ...MUX_C - STATUS/CSENSE multiplexer pin - selection of one signal (ST0/CS0 ... ST7/CS7) to MUX ST/CS pin MUX_C MUX_B MUX_A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ST0/CS0 signal is transferred to MUX ST/CS pin (default) ST1/CS1 signal is transferred to MUX ST/CS pin ST2/CS2 signal is transferred to MUX ST/CS pin ST3/CS3 signal is transferred to MUX ST/CS pin ST4/CS4 signal is transferred to MUX ST/CS pin ST5/CS5 signal is transferred to MUX ST/CS pin ST6/CS6 signal is transferred to MUX ST/CS pin ST7/CS7 signal is transferred to MUX ST/CS pin CS_MONITOR1, CS_MONITOR 0: select one out of the 4 different ChipSelectTimeouts, served by CSN. The internal counter is reset by the rising edge of the CSN pin. When a Timeout occurs the device enters FAIL SAFE mode (LimpHome). CS_MONITOR1 0 0 CS_MONITOR0 0 1 max time for serving the CSN set to 50ms max time for serving the CSN set to 100ms (default) Doc ID 15872 Rev 3 29/41 SPI L99PD08 1 1 Table 26. Bit 7 CH7 0 1 max time for serving the CSN set to 200ms max time for serving the CSN set to 400ms ON_OFF register, hex01 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 Ox channel is switched off (default) 1 Ox channel is switched on CHx Output Ox Table 27. Bit 7 CH7 DEV_TYPE register, hex02 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 1 Note: Digital device is connected to device output (default) Analog device is connected to device output If a channel is in ON-state (ON_OFF reg = `1'), the corresponding DEV_TYPE register is write protected. PWM_EN register, hex03 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 Table 28. Bit 7 CH7 CHx 0 1 If OUTx in ON_OFF register is 1, OUTx is switched in steady state mode (default) If OUTx in ON_OFF register is 1, OUTx is switched in PWM mode CHx Enables PWM mode on output Ox Table 29. Bit 7 CH7 CLK_SEL register, hex04 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 The external clock source signal CLK_IN0 is selected for internal generation of PWM signal for OUTx channel. The PWM period is the received clock signal divided by 256 (default). 30/41 Doc ID 15872 Rev 3 L99PD08 SPI 1 The external clock source signal CLK_IN1 is selected for internal generation of PWM signal for OUTx channel. The PWM period is the received clock signal divided by 256. CHx PWM input signal selection for Ox channel Table 30. Bit 7 CH7 ASDT register, hex05 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 1 Automatic shutdown of thermal cycling is switched off Automatic shutdown of thermal cycling is switched on (default) Setting the ASDT bit to 1 means the automatic shutdown function is switched ON and the channel is switched OFF after setting the OT_FAULT (over temperature or power limitation) bit to 1. This can happen with a digital HSD either reaching the thermal shut down (or power limitation) or detecting ambiguous failure with OT_FAULT. Note, that the thermal shutdown is detected at 6mA regardless of the current range After OT_FAULT register is "Read & Cleared" (clear status code, see 6.6), the device activates the corresponding channel after clear according to setting. Table 31. Bit 7 CH7 DET_DIAG register, hex06 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 Automatic detailed diagnosis is disabled. Automatic detailed diagnosis is enabled, switching off is activated when failure in onstate is detected. The purpose is to have short off-state (27 s typ +/-6us) in order to have detailed information of the failure. The delay between discriminating pulses is 4 ms (default). 1 Doc ID 15872 Rev 3 31/41 SPI L99PD08 Table 32. Bit 7 CH7-1 BLK_TIME1 register, hex07 (RW-Type) Bit 6 CH7-0 Bit 5 CH6-1 Bit 4 CH6-0 Bit 3 CH5-1 Bit 2 CH5-0 Bit 1 CH4-1 Bit 0 CH4-0 Table 33. Bit 7 CH3-1 BLK_TIME2 register, hex08 (RW-Type) Bit 6 CH3-0 Bit 5 CH2-1 Bit 4 CH2-0 Bit 3 CH1-1 Bit 2 CH1-0 Bit 1 CH0-1 Bit 0 CH0-0 BLK_TIME 0 0 The blank time is not active after activation of the related channel. (CHx-1;CHx-0) 0 1 The blank time is active after activation of the related channel and set to 15 ms (minimum). 1 0 The blank time is active after activation of the related channel and set to 70 ms (minimum). 1 1 The blank time is active after activation of the related channel and set to 200ms (minimum) (default). The duration of the blank time can be set to three different timings in order to avoid any wrong detection of failures during an inrush phase when switching on the load. During this time the diagnostics doesn't report any failures. Note: The Blanking time is started by turning the selected channel on. Write command to address 0x00 with a `1' (former state `0' => OFF). If a channel is in on-state (ON_OFF reg = `1'), the corresponding BLK_TIMEx register is write protected. Table 34. Bit 7 CH7 TD_SENSE register, hex09 (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 1 the diagnosis is activated 300 s(min) after the rising edge of the output OUTx the diagnosis is activated 600 s(min) after the rising edge of the output OUTx (default) Note: This blanking time is just used for analog devices and is related to the analog device connected to the device (see VIP specification). If a channel is in ON-state (ON_OFF reg = `1'), the corresponding TD_SENSE register is write protected. Table 35. Bit 7 CH7 CFR register, hex0A (RW-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 32/41 Doc ID 15872 Rev 3 L99PD08 The variable gain of Current sense feedback ratio for ST/CS channels (ST0/CS0 ... ST7/CS7). It is applied between the ST/CSx input signal current and both, internal diagnostics and MUX_CS/ST signal current. CFR 0 1 SPI the gain of current sense signal to internal current comparator is 1:10 (default) the gain of current sense signal to internal current comparator is 1:1 Table 36. Bit 7 CH7-1 OLOVL_TH_1 register, hex0B (RW-Type) Bit 6 CH7-0 Bit 5 CH6-1 Bit 4 CH6-0 Bit 3 CH5-1 Bit 2 CH5-0 Bit 1 CH4-1 Bit 0 CH4-0 Open-load threshold values for ST/CS channels (ST4/CS4 ... ST7/CS7). CH 1,0 0 x 10 11 50 A(CFL=0), 5 A(CFL=1) (default) 100 A(CFL=0), 10 A(CFL=1) 400 A(CFL=0), 40 A(CFL=1) Overload threshold values for ST/CS channels (ST4/CS4 ... ST7/CS7). CH 1,0 0 0 01 10 11 Table 37. Bit 7 CH3-1 1.2 mA(CFL=0), 120 A(CFL=1) (default) 2.4 mA(CFL=0), 240 A(CFL=1) 3.6 mA(CFL=0), 360 A(CFL=1) 6.0 mA(CFL=0), 600 A(CFL=1) OLOVL_TH_2 register, hex0C (RW-Type) Bit 6 CH3-0 Bit 5 CH2-1 Bit 4 CH2-0 Bit 3 CH1-1 Bit 2 CH1-0 Bit 1 CH0-1 Bit 0 CH0-0 Open-load threshold values for ST/CS channels (ST0/CS0 ... ST3/CS3). CH 1,0 0 x 10 11 50 A(CFL=0), 5 A(CFL=1) (default) 100 A(CFL=0), 10 A(CFL=1) 400 A(CFL=0), 40 A(CFL=1) Overload threshold values for ST/CS channels (ST0/CS0 ... ST3/CS3). CH 1,0 0 0 01 10 11 1.2 mA(CFL=0), 120 A(CFL=1) (default) 2.4 mA(CFL=0), 240 A(CFL=1) 3.6 mA(CFL=0), 360 A(CFL=1) 6.0 mA(CFL=0), 600 A(CFL=1) Doc ID 15872 Rev 3 33/41 SPI Table 38. Bit 7 b7 L99PD08 DUTY_CH 0 - DUTY_CH 7 Registers, hex10 - hex17 (RW-Type) Bit 6 b6 Bit 5 b5 Bit 4 b4 Bit 3 b3 Bit 2 b2 Bit 1 b1 Bit 0 b0 Output PWM duty cycle selection, one register per channel. Active only if PWM_EN signal is set for dedicated output. b7 ... b1 - PWM duty cycle of this channel (256 levels, default value - 50% DC, 80H) Note: The values of the duty cycle and the Phase will be captured and executed with the end of the write command. Be aware, that an unwanted PWM can be generated during this phase. PHASE_CH 0 - PHASE_CH7 Registers, hex18 - hex1F (RW-Type) Bit 6 b6 Bit 5 b5 Bit 4 b4 Bit 3 b3 Bit 2 Bit 1 Bit 0 - Table 39. Bit 7 b7 Output PWM phase shift selection, one register per channel. This feature will improve the power net characteristic during PWM mode. b7 ... b3 - phase shift of this channel related to the length of 1 PWM period (5 bits - 32 levels). Default values: PHASE_CH0 PHASE_CH1 PHASE_CH2 PHASE_CH3 PHASE_CH4 PHASE_CH5 PHASE_CH6 PHASE_CH7 Note: 0x00h 0x20h 0x40h 0x60h 0x80h 0xA0h 0xC0h 0xE0h (0/32) (4/32) (8/32) (12/32) (16/32) (20/32) (24/32) (28/32) The values of the duty cycle and the phase will be captured and executed with the end of the write command. Be aware, that an unwanted PWM can be generated during this phase. CHANNEL_FB Registers, hex2E (R-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 Table 40. Bit 7 CH7 CHx 0 1 channel CH x is off channel CH x is on 34/41 Doc ID 15872 Rev 3 L99PD08 Table 41. Bit 7 - SPI AUX_STATUS Registers, hex2F (RC-Type) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CLK_IN1 Warm Bit 0 CLK_IN0 Warm CS_time50% CS_timeout CLK_IN0 Warn, CLK_IN1 Warn: the corresponding warn bit is set when the input frequency is below 5kHz (fPWMmin_set = 19 Hz) and reset when the frequency is above 7 kHz fPWMmin_reset = 28 Hz. The hysteresis was implemented not to get a flickering on the PWM output. If the warn bit is set the PWM is generated by an internally generated signal (f = 122 Hz). The warn bit does not set the global error flag. CLK_INx Warn 0 1 CS_timeout CS_time50% Table 42. Bit 7 CH7 input clock frequency fCLK_INx > 7 kHz. input clock frequency fCLK_INx < 5 kHz (fPWMmin < 19 Hz). The internal generated PWM clock signal is used. this bit is set when a CS-timeout occurred. It has to be cleared by a clear command (Op code b10) this bit is set when 50% of the CS-timeout time is reached. OT_FAULT Registers, hex30 (RC-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 on channel CHx wasn't detected dedicated failure 1 on channel CHx was detected dedicated failure Note: If a digital device and no detailed diagnosis is selected, also ambiguous failures are reflected in this register (channel is turned off if ASDT is selected). OL_FAULT Registers, hex31 (RC-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 Table 43. Bit 7 CH7 CHx 0 on channel CHx wasn't detected dedicated failure 1 on channel CHx was detected dedicated failure Note: 1 In digital mode, the OL failure can not be cleared in off-state when detailed diagnosis is disabled. To clear the OL bit, the detailed diagnosis has to be enabled or the failure has to be removed and cleared in on-state. If a digital device and no detailed diagnosis is selected, also ambiguous failures are reflected in this register. 2 Doc ID 15872 Rev 3 35/41 SPI Table 44. Bit 7 CH7 L99PD08 STK_FAULT Registers, hex32 (RC-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 on channel CHx wasn't detected dedicated failure 1 on channel CHx was detected dedicated failure Table 45. Bit 7 CH7 OVL_FAULT Registers, hex33 (RC-Type) Bit 6 CH6 Bit 5 CH5 Bit 4 CH4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 CHx 0 on channel CHx wasn't detected dedicated failure 1 on channel CHx was detected dedicated failure 36/41 Doc ID 15872 Rev 3 L99PD08 Package and packing information 7 7.1 Package and packing information ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.2 LQFP32 mechanical data Figure 11. LQFP32 outline ccc C D D1 D3 24 25 b E3 32 9 Pin 1 identification A1 1 8 L K E1 E 17 16 L1 A A2 c 5V_ME Table 46. LQFP32 mechanical data millimeters Symbol Min A A1 A2 b c D D1 D3 0.05 1.35 0.3 0.09 8.8 6.8 9 7 5.6 1.4 0.37 Typ Max 1.6 0.15 1.45 0.45 0.2 9.2 7.2 Doc ID 15872 Rev 3 37/41 Package and packing information Table 46. LQFP32 mechanical data (continued) millimeters Symbol Min E E1 E3 e L L1 k ccc 0.0 0.45 8.8 6.8 Typ 9 7 5.6 0.8 0.6 1 3.5 7.0 0.1 L99PD08 Max 9.2 7.2 0.75 7.3 LQFP32 packing information The devices can be packed in tube or tape and reel shipments (see the Summary device on page 1 for packaging quantities). Figure 12. LQFP32 tape and reel shipment (suffix "TR") 38/41 Doc ID 15872 Rev 3 L99PD08 Figure 13. LQFP32 tray shipment (no suffix) Package and packing information Doc ID 15872 Rev 3 39/41 Revision history L99PD08 8 Revision history Table 47. Date 16-Jun-2009 Document revision history Revision 1 Initial release. Updated Table 7: Supply, Table 11: Current sense/status inputs, Table 12: MUX_ST/CS output, Table 13: Current MUX_ST/CS ratio, Table 14: Current sense diagnostic thresholds and Table 16: DC characteristics. Changed status device from target specification to datasheet. Changes 16-Jul-2009 2 09-Apr-2010 3 40/41 Doc ID 15872 Rev 3 L99PD08 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15872 Rev 3 41/41 |
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